The present invention relates to methods and apparatus for testing of faults and defects within electronic devices, such as semiconductor memory circuits.
Electronic devices such as memory chips can contain undesired faults and defects that arise due to imperfections in manufacturing processes. These faults and defects include open circuits, short circuits, and out-of-tolerance components. Testing for these faults during manufacture is impractical and costly in light of the new process technologies currently being used to manufacture electronic circuits and devices. Therefore, self-test circuits have been incorporated within modern circuits and devices in order to improve reliability, to eliminate defective and faulty circuits and devices, and to reduce cost.
One example of an incorporated self-test circuit measures the quiescent DC power supply current. This method is referred to as the IDDQ method. In the IDDQ method, power supply currents outside a predetermined range indicate a faulty circuit or device. Examples of this method can be found in U.S. Pat. Nos. 6,342,790, 6,301,168, and 6,144,214. In general, an apparatus incorporating quiescent DC power supply current for self-test monitors the current from a power supply using a current sensor. Therefore, the apparatus effectively monitors the supply current delivered to the Device Under Test (DUT) and transmits a final output signal that is in proportion to the supply current delivered to the DUT. The final output signal is analyzed to determine whether or not any faults exist in the DUT.
The IDDQ method, however, requires quiescent defect currents of appreciable magnitude relative to the quiescent currents in fault-free circuits and devices. But the difference between faulty currents and fault-free currents may be negligible in many components. Moreover, quiescent leakage currents associated with emerging technologies are large enough to render these IDDQ methods ineffective in detecting faulty circuits.
These emerging technologies include deep sub-micron integrated circuit technology. Sub-micron circuits have increased leakage currents and associated large DC supply currents that greatly reduce the effectiveness of the IDDQ methods. Additional challenges to testing of sub-micron circuits include significant increases in circuit size, rapid increases in clock frequencies, the dominance of the interconnect delay, the transmission-line behavior of interconnects, the reduced level of the power supply voltage, the increase in leakage currents, the increase in power consumption, and the increased sensitivity of circuit arrangements to process defects. Therefore, fault monitoring circuitry was developed for measurement of the transient power supply current. Methods employing such circuitry are referred to as IDDT methods wherein transient power supply currents outside a predetermined range indicate a faulty circuit or device.
U.S. Pat. No. 6,414,511 discloses an example of an IDDT method. In general, an apparatus incorporating transient power supply current for self-test monitors the current from the power supply using a current sensor. Therefore, the apparatus effectively monitors the transient supply current delivered to the Device Under Test (DUT) and transmits a final output signal that is in proportion to the transient supply current of the DUT. The final output signal is analyzed to determine whether or not any faults exist in the DUT.
Prior implementations of the IDDT methods, however, do not adequately address the need for large bandwidths to handle the extremely short duration underlying transients in deep sub-micron technology. These prior methods have relied on dubious and inadvertent integration of the high-speed transients (i.e., lowpass filtering of transients) to allow slower circuits to process the transients. In such methods, the extremely high-speed transients native to the DUT are the transients being observed and measured for the purpose of detecting faulty circuits. The associated high-speed transients have led to over-simplified and questionable solutions, which have not found application in industry. Moreover, the bandwidth of such transients in digital circuits are by their very nature faster than the highest clock speeds of the circuit, since the duration of the transient is commonly shorter than the logic rise and fall times.
Therefore, a need exists to find alternative methods and apparatus that effectively and practically utilize transient power supply currents in testing devices and circuits for faults and defects. Suitable methods and apparatus should be capable of testing with little disruption of the circuits under test, with little added hardware, and with minimal effect on manufacturing costs. In addition, suitable methods and apparatus should be capable of the necessary testing at lower speeds and bandwidths to be advantageous for implementations in circuits, devices, and systems.
The present invention is directed to apparatus and methods for detecting faults in circuits, devices, and systems. Suitable circuits, devices and systems include integrated circuits for memory cells, combinational logic, mixed-signal circuits, analog circuits, and the receiver and transmitter portions of cellular phone handsets. In memory chips, the transient supply current apparatus and methods can be used to detect faulty memory cells and memory chips. Similarly, transient supply current apparatus and methods can be used to detect faulty devices and sub-circuits within combinational logic, mixed-signal circuits, and analog circuits.
In one embodiment of the present invention, an apparatus for controlled pulse-width transient power supply testing is used. The apparatus includes a current measuring device, a Device Under Test (DUT) such as a Static Random Access Memory (SRAM) cell or a bank of memory cells, and input control signals including a test-pulse generator and control signals to set signal levels within the DUT. Suitable current measurement devices are capable of measuring the transient current delivered to the DUT. The test-pulse generator includes at least one output that is electrically coupled to and in communication with the DUT. In operation, the test-pulse generator controls the DUT to generate a transient power supply current within a sub-circuit of the DUT. This transient power supply current is of a controlled pulse-width and duration. The generated transient current is monitored and measured by the current measurement device. The measured transient current is then analyzed for indications of defects or faults in the DUT.
In another embodiment of the present invention, digital portions of the DUT are analyzed. In this embodiment, the DUT is exposed to a plurality of input control signals. One or more signals from this plurality of input control signals are selected and set to cause signal levels internal to the digital portions of DUT to have values that are intermediate to the logic levels. For example, the logic levels are about 0 volts and about 5 volts and the intermediate voltage level within the digital portion is about 2.5 volts. These intermediate values in conjunction with the other input control signals help induce DUT power supply current of a controlled pulse-width and duration that is then monitored for deviations from values for fault-free devices, such deviations indicating a faulty circuit.
In another embodiment of the present invention, the apparatus includes a first resistor which is coupled into the supply current lead of the DUT, and a high pass filter containing a capacitor and a second resistor is electrically coupled to the DUT supply line between the DUT and the first resistor. The second resistor is then electrically coupled to a cascade of a plurality of wideband voltage amplifiers. The output of the amplifiers is electrically coupled to a comparator circuit. In operation, the first resistor converts the supply current transients to voltage transients. The current transients can be native to the DUT or deliberately introduced. These voltage transients are then AC coupled through the capacitor and second resistor to reject the DC voltage associated with the high leakage current while preserving the shape and magnitude of the voltage pulses. These voltage pulses, i.e. the IDDT supply current pulses, are amplified by the plurality of differential, wideband amplifiers. The comparator assesses the output from the amplifiers to determine normal or abnormal operation of the DUT.
The apparatus and methods of the present invention provide the unexpected results and advantages of direct observability into the switching profile of the DUT. In addition, the test time is significantly reduced since it is not necessary for a circuit to reach steady-state or static supply current operation following test stimuli. The apparatus and method of the present invention eliminate measurement problems associated with quiescent current and are particularly well suited for emerging sub-micron technologies. Since faults can be assessed directly form the transient supply current, the need for separate read operations is eliminated. The apparatus and methods of the present invention detect a wide range of faults and defects including resistive opens and shorts, capacitive opens, pattern sensitive faults, tunneling, and crosstalk. The method and apparatus of the present invention substantially reduce test costs and improve fault coverage. The need to implement costly test methods such as separate test pins or supply partitioning to overcome limitations of large leakage currents is eliminated.